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E2O0012-27-X2
Semiconductor MSM82C84A-2RS/GS/JS
Semiconductor CLOCK GENERATOR AND DRIVER
This version: Jan. 1998 MSM82C84A-2RS/GS/JS Previous version: Aug. 1996
GENERAL DESCRIPTION
The MSM82C84A-2RS/GS is a clock generator designed to generate MSM80C86A-10 and MSM80C88A-10 system clocks of 8MHz. Due to the use of silicon gate CMOS technology, standby current is only 40 mA (MAX.), and the power consumption is very low with 16 mA (MAX.) when a 8 MHz clock is generated.
FEATURES
* Operating frequency of 6 to 24 MHz (CLK output 2 to 8 MHz) * 3 m silicon gate CMOS technology for low power consumption * Built-in crystal oscillator circuit * 3 V to 6 V single power supply * Built-in synchronized circuit for MSM80C86A-10 and MSM80C88A-10 READY and RESET * TTL compatible * Built-in Schmitt trigger circuit (RES input) * 18-pin Plastic DIP (DIP18-P-300-2.54): (Product name: MSM82C84A-2RS) * 20-pin Plastic QFJ (QFJ20-P-S350-1.27): (Product name: MSM82C84A-2JS) * 24-pin Plastic SOP (SOP24-P-430-1.27-K): (Product name: MSM82C84A-2GS-K)
FUNCTIONAL BLOCK DIAGRAM
RES x1 x2 F/C EFI CSYNC RDY1 AEN1 AEN2 RDY2 ASYNC
C
D C
Q
RESET OSC
Crystal Oscillator
1 3
S Y N C
1 2
S Y N C
PCLK
CLK
CO
D (F1)
Q
D (F2)
Q
READY
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PIN CONFIGURATION (TOP VIEW)
18 pin Plastic DIP
CSYNC PCLK AEN1 RDY1 READY RDY2 AEN2 CLK GND
1 2 3 4 5 6 7 8 9
18 VCC 17 X1 16 X2 15 ASYNC 14 EFI 13 F/C 12 OSC 11 RES 10 RESET
24 pin Plastic SOP
CSYNC PCLK NC AEN1 RDY1 READY NC RDY2 AEN2
1 2 3 4 5 6 7 8 9
24 23 22 21 20 19 18 17 16 15 14 13
Vcc X1 X2 NC ASYNC EFI NC F/C OSC NC RES RESET
NC 10 CLK 11 GND 12
CSYNC
PCLK
AEN1
20 VCC
20 pin Plastic QFJ
RDY1 4 READY 5 RDY2 6 AEN2 7 NC 8 18 X2 17 ASYNC 16 EFI 15 F/C 14 NC
GND 10
RESET 11
RES 12
OSC 13
CLK
9
19 X1
3
2
1
(NC not connected)
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ABSOLUTE MAXIMUM RATINGS
Parameter Supply Voltage Input Voltage Output Voltage Storage Temperature Power Dissipation Symbol VCC VIN VOUT TSTG PD Condition Respect to GND -- Ta = 25C 0.8 Rating
MSM82C84A-2RS/JS MSM82C84A-2GS
Unit V V V C 0.7 W
-0.5 to +7 -0.5 to VCC +0.5 -0.5 to VCC +0.5 -55 to +150
OPERATING RANGES
Parameter Supply Voltage Operating Temperature Symbol VCC Top Range 3 to 6 -40 to +85 Unit V C
RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage Operating Temperature "L" Level Input Voltage "H" Level Input Voltage (except RES) "H" Level Input Voltage (RES) Symbol VCC Top VIL VIH Min. 4.5 -40 -0.5 2.2 0.6*VCC Typ. 5 +25 -- -- Max. 5.5 +85 +0.8 VCC +0.5 Unit V C V V
DC CHARACTERISTICS
(VCC = 5 V 10%, Ta = -40 to 85C) Parameter "L" Level Output Voltage (CLK) "L" Level Output Voltage (Others) "H" Output Voltage (CLK) "H" Output Voltage (Others) RES Input Hysteresis Input Leak Current (Except ASYNC) Input Current (ASYNC) Standby Supply Current Operating Supply Current Input Capacitance Symbol V OL VOL VOH VOH VIHR -VILR ILI ILIA ICCS ICC CIN 0 VIN VCC 0 VIN VCC Note 1 f = 24 MHz, CL= O PF f =1 MHz Condition IOL = 4 mA IOL = 2.5 mA IOH = -4 mA IOH = -1 mA Min. -- -- VCC -0.4 VCC -0.4 0.2*VCC -1 -100 -- -- -- Max. 0.4 0.4 -- -- -- +1 +10 40 16 7 Unit V V V V V mA mA mA mA pF
Note:
1. X1 VCC - 0.2 V, X2 0.2 V F/C VCC - 0.2 V, ASYNC = VCC or open VIH VCC - 0.2 V, VIL 0.2 V 3/18
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AC CHARACTERISTICS
(1)
Parameter EFI "H" Pulse Width EFI "L" Pulse Width EFI Cycle Time Crystal Oscillator Frequency Set up Time of RDY 1 or RDY 2 to CLK Falling Edge (Active) Set up Time of RDY 1 or RDY 2 to CLK Rising Edge (Active) Set up Time of RDY 1 or RDY 2 to CLK Falling Edge (Inactive) Hold Time of RDY 1 or RDY 2 to CLK Falling Edge Set up Time of ASYNC to CLK Falling Edge Hold Time of ASYNC to CLK Falling Edge Set up Time of AEN 1 (AEN 2) to RDY 1 (RDY 2) Rising Edge Hold Time of AEN 1 (AEN 2) to CLK Falling Edge Set up Time of CSYNC to EFI Rising Edge Hold Time of CSYNC to EFI Rising Edge CSYNC Pulse Width Set up Time of RES to CLK Falling Edge Hold Time of RES to CLK Falling Edge Input Rising Edge Time Input Falling Edge Time Symbol tEHEL tELEH tELEL -- tR1VCL tR1VCH tR1VCL tCLR1X tAYVCL tCLAYX tA1R1V tCLA1X tYHEH tEHYL tYHYL tI1HCL tCLI1H tILIH tIHIL Min. 13 17 36 6 35 35 35 0 50 0 15 0 20 10 2 tELEL 65 20 -- -- Max. -- -- -- 24 -- -- -- -- -- -- -- -- -- -- -- -- -- 15 15 Unit ns ns ns MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (VCC = 5 V 10%, Ta = -40 to 85C) Conditions 90% to 90% 10% to 10% -- -- ASYNC = High ASYNC = Low -- -- -- -- -- -- -- -- -- -- -- -- -- Output Load Capacitance CLK output CL = 100 pF Others 30 pF
Note: Parameters where timing has not been indicated in the above table are measured at VL = 1.5 V and VH = 1.5 V for both inputs and outputs.
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AC CHARACTERISTICS
(2)
(VCC = 5 V 10%, Ta = -40 to 85C) Parameter CLK Cycle Time CLK "H" Pulse Width CLK "L" Pulse Width CLK Rising and Falling Edge Times PCLK "H" Pulse Width PCLK "L" Pulse Width Time from READY Falling Edge to CLK Falling Edge Time from READY Rising Edge to CLK Rising Edge Delay from CLK Falling Edge to RESET Falling Edge Delay from CLK Falling Edge to PCLK Rising Edge Delay from CLK Falling Edge to PCLK Falling Edge Delay from OSC Falling Edge to CLK Rising Edge Delay from OSC Falling Edge to CLK Falling Edge Output Rising Edge Time (Except CLK) Output Falling Edge Time (Except CLK) Symbol tCLCL tCHCL tCLCH tCH1CH2 tCL2CL1 tPHPL tPLPH tRYLCL tRYHCH tCLIL tCLPH tCLPL tOLCH tOLCL tOLOH tOHOL -- -- -- 1.0 V to 3.5 V -- -- -- -- -- -- -- -- -- 0.8 V to 2.2 V 2.2 V to 0.8 V Output Load Capacitance CLK Output CL = 100 pF Others 30 pF Conditions Min. 125 1 T +2 3 CLCL 2 T -15 3 CLCL -- TCLCL -20 TCLCL -20 -8 2 T -15 3 CLCL -- -- -- -5 2 -- -- Max. -- -- -- 10 -- -- -- -- 40 22 22 22 35 15 15 Unit ns ns ns ns ns
ns ns ns ns ns ns ns ns ns
Note: Parameters where timing has not been indicated in the above table are measured at VL = 1.5 V and VH = 1.5 V for both inputs and outputs.
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PIN DESCRIPTION
Pin Symbol Name Input/Output Function Synchronizing signal for output of in-phase CLK signals when more than one MSM82C84A-2 is used. The internal counter is reset when this signal is at high level, and a high level CLK output is generated. The internal counter is subsequently activated and a 33% duty CLK output is generated when this signal is switched to low level. When this signal is used, external synchronization of EFI is necessary. When the internal oscillator is used, it is necessary for this pin to be kept to be low level. This peripheral circuit clock signal is output in a 50% duty cycle at a frequency half that of the clock signal. The AEN1 signal enables RDY1, and the AEN2 signal RDY2. The respective RDY inputs are activated when the level applied to these pins is low. Although two separate inputs are used in multi-master systems, only the AEN which enables the RDY input to be used is to be switched to low level in the case of not using multi-master systems. Completion of data bus reading and writing by the device connected to the system data bus is indicated when one of these signals is switched to high level. The relevant RDY input is enables only when the corresponding AEN is at low level. This signal is obtained by synchronizing the bus ready signal with CLK. This signal is output after guaranteeing the hold time for the CPU in phase with the RDY input. This signal is the clock used by the CPU and peripheral devices connected to the CPU system data bus. The output waveform is generated in a 33% duty cycle at a frequency 1/3 the oscillating frequency of the crystal oscillator connected to the X1 and X2 pins, or at a frequency 1/3 the EFI input frequency. This low-level active input is used to generate a CPU reset signal. Since a Schmitt trigger is included in the input circuit for this signal, "power on resetting" can be achieved by connection of a simple RC circuit. This signal is obtained by CLK synchronization of the input signal applied to RES and is output in opposite phase to the RES input. This signal is applied to the CPU as the system reset signal. This signal selects the fundamental signal for generation of the CLK signal. The CLK is generated from the crystal oscillator output when this signal is at low level, and from the EFI input signal when at high level. The signal applied to this input pin generaters the CLK signal when F/C is at high level. The frequency of the input signal needs to be three times greater than the desired CLK frequency. Crystal oscillator connections. The crystal oscillator frequency needs to be three times greater than the desired CLK frequency. Crystal oscillator output. This output frequency is the same as the oscillating frequency of the oscillator connected to the X1 and X2 pins. As long as a Xtal oscillator is connected to the X1 and X2 pins, this output signal can be obtained independently even if F/C is set to high level to enable the EFI input to be used CLK generation purpose.
CSYNC
Clock Synchronization Single
Input
PCLK AEN1 AEN2
Peripheral Clock Output
Output
Address Enable Signals
Input
RDY1 RDY2
Bus Ready Signals
Input
READY
Ready Output
Output
CLK
Clock Output
Output
RES
Reset in
Input
RESET
Reset Output Clock Select Signal
Output
F/C
Input
EFI
External Clock Signal Crystal Oscillator Connecting Pins Crystal Resonator Output
Input
X1, X 2
Input
OSC
Output
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Pin Symbol
Name Ready synchronization select signal -- --
Input/Output
Function Signal for selection of the synchronization mode of the READY signal generator circuit. When this signal is at low level, the READY signal is generated by double synchronization. And when at high level, the READY signal is generated by single synchronization. This pin is equipped with internal pull-up resistor. +5 V power supply GND
ASYNC
Input
VCC GND
-- --
TIMING DIAGRAM
CLK * PCLK * OSC Waveforms
tELEL EFI tELEH OSC tEHYL CSYNC tYHYL tOLCH tYHEH tCLCL tOLCL CLK tCLCH tPHPL PCLK tPLPH tCLPH tCHCL tCH1CH2 tEHEL
tCLPL tCL2CL1
RESET Waveform
CLK tI1HCL tCLI1H RES
tCLIL RESET
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Semiconductor READY Waveform (ASYNC = L)
tR1VCH CLK tCLR1X RDY1 - 2 tA1R1V AEN1 - 2 ASYNC tAYVCL
MSM82C84A-2RS/GS/JS
tR1VCL
tCLR1X
tCLA1X
tCLAYX
READY tRYHCH tRYLCL
READY Waveform (ASYNC = H)
tR1VCL CLK tCLR1X RDY1 - 2 tA1R1V AEN1 - 2 ASYNC tAYVCL tCLAYX tCLA1X tCLR1X tR1VCL
tRYHCH READY tRYLCL
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MSM82C84A-2RS/GS/JS
OPERATIONAL DESCRIPTION
(1) Oscillator Circuit The MSM82C84A-2 internal oscillator circuit can be driven by connecting a crystal oscillator to the X1 and X2 pins. The frequency of the crystal oscillator in this case needs to be three times greater than the desired CLK frequency. Since the oscillator circuit output (the same output as for the crystal resonator frequency) appears at the OSC pin, independent use of this output is also possible. Oscillator Circuit Example
Note: Because Oscillator circuit and values depend on crystal oscillator characteristics, OKI recommends to make contact with crystal oscillator vendor to determine the best circuit and values for customers' application.
X1 OSC C1 C2 MSM 82C84A-2 X2
Crystal Oscillator
When input frequency is 6 to 15 MHz C1 = C2 = 33 pF When input frequency is 15 to 24 MHz C1 = C2 = 10 pF
(2) Clock Generator Circuit This circuit generates two clock outputs-CLK obtained by dividing the input external clock or crystal oscillator circuit output by three, and PCLK obtained by halving CLK. CLK and PCLK are generated from the external clock applied to the EFI pin when F/C is at high level, and are generated from the crystal oscillator circuit when at low level.
(3) Reset Circuit Since a Schmitt trigger circuit is used in the RES input, the MSM82C84A-2 can be reset by "power on" by connection to a simple RC circuit. If the MSM80C86A-10 or MSM80C88A-10 is used as the CPU in this case, it is necessary to keep the RES input at low level for at least 50 ms after Vcc reaches the 4.5V level.
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MSM82C84A-2RS/GS/JS
The READY signal generator circuit can be set to synchronization mode by ASYNC. (i) When ASYNC is at low level The RDY input is output as the READY signal by double synchronization. The high-level RDY input is synchronized once by the rising edge of the CLK of the first stage flip-flop (F1 in the circuit diagram), and then synchronized again by the falling edge of the CLK of the next stage flip-flop (F2 in the circuit diagram), resulting in output of a high-level READY output signal (see diagram below). The low-level RDY input is synchronized directly by the falling-edge of the CLK of the next stage flip-flop, resulting in output of a low-level READY output signal (see diagram below).
CLK RDY
READY
(ii) When ASYNC is at high level The RDY input is output as the READY signal by single synchronization. Both low-level and high-level RDY inputs are synchronized by the falling edge of the CLK of the next stage flip-flop, resulting output of respective low-level and high-level READY output signals (see diagram below).
CLK RDY
READY
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EXAMPLE OF USE (CSYNC)
The MSM82C84A-2 1/3 frequency divider counter is unsettled when the power is switched on. Therefore, the CSYNC pin has been included to synchronize CLK with another signal. When CSYNC is at high level, both CLK and PCLK are high-level outputs. If CSYNC is then switched to low level, CLK is output from the next input clock rising edge, and is divided by 3. If CSYNC has not been synchronized with the input clock, use the following circuit to achieve the required synchronization
External Sychronizing Signal External Clock Signal (EFI)
D CK
Q
D CKO
Q
CSYNC MSM 82C84A-2 EFI CLK
CLK
When an external clock EFI is used as the clock source
External Sychronizing Signal
D CK
Q
D CKO
Q
CSYNC
X2 MSM 82C84A-2 OSC
When the crystal oscillator is used as the clock source
NOTES ON USE
X1 F/C CLK
CLK
The MSM82C84A-2 cannot be used if the MSM80C86A-10 or MSM80C88A-10 is used within the range of 8 MHz < operating frequency 10 MHz.
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NOTICE ON REPLACING LOW-SPEED DEVICES WITH HIGH-SPEED DEVICES
The conventional low speed devices are replaced by high-speed devices as shown below. When you want to replace your low speed devices with high-speed devices, read the replacement notice given on the next pages.
High-speed device (New) M80C85AH M80C86A-10 M80C88A-10 M82C84A-2 M81C55-5 M82C37B-5 M82C51A-2 M82C53-2 M82C55A-2
Low-speed device (Old) M80C85A/M80C85A-2 M80C86A/M80C86A-2 M80C88A/M80C88A-2 M82C84A/M82C84A-5 M81C55 M82C37A/M82C37A-5 M82C51A M82C53-5 M82C55A-5
Remarks 8bit MPU 16bit MPU 8bit MPU Clock generator RAM.I/O, timer DMA controller USART Timer PPI
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Differences between MSM82C84A and MSM82C84A-5/MSM82C84A-2 1) Manufacturing Process All these devices use a 3 m Si-Gate CMOS process technology. The chip size of these devices is same. The chip of the MSM82C84A-5 is entirely identical to that of the MSM82C84A-2. 2) Functions
Item Internal processing of ASYNC pin Notes on use
MSM82C84A Normal CMOS input pin The pin should have a pullup or pulldown resistor if it is unused.
MSM82C84A-5/-2 Input pin with built-in pull up resistor The value of pulldown resistor (when used) is limited. (See page 3.)
3) Electrical Characteristics 3-1) DC Characteristics Parameter ''L''Level Output Voltage (CLK) ''L''Level Output Voltage (Other than CLK) ''H''Level Output Voltage (CLK) ''H''Level Output Voltage (Other than CLK) RES Input Hysteresis Width Input Current (ASYNC) Input Leak Current Supply Current (Standby) Symbol VOL VOL VOH VOH VIHRVILR ILIA ILI ICCS MSM82C84A 0.45 V maximum (+5 mA) 0.45 V maximum (+5 mA) 3.7 V minimum (-1 mA) 3.7 V minimum (-1 mA) 0.25 V minimum -10 mA to +10 mA -10 mA to +10 mA 100 mA maximum MSM82C84A-5/-2 0.40 V maximum (+4 mA) 0.40 V maximum (+2.5 mA) VCC-0.1 V minimum (-4 mA) VCC-0.1 V minimum (-1 mA) 0.2 VCC min -100 mA~+10 mA -1 mA~+1 mA 40 mA maximum
As shown above, the MSM82C84A-5/MSM82C84A-2 satisfies the characteristics (except for VOL and input current (ASYNC) of the MSM82C84A.
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3-2) AC Charasteristics 1) MSM82C84A and MSM82C84A-2
Parameter Input Rise Time Input Fall Time CLK High Time CLK Low Time CLK Rise/Fall Time PCLK High Time PCLK Low Time READY Falling to CLK Rising Symbol tILIH tILIH tCHCL tCLCH tCH1CH2 tCL1CL2 tPHPL tPLPH tRYHCH MSM82C84A 20 ns maximum 20 ns maximum 65 ns minimum 119 ns minimum 15 ns maximum 180 ns minimum 180 ns minimum 114 ns minimum
MSM82C84A-2RS/GS/JS
MSM82C84A-2 15 ns maximum 15 ns maximum 1/3 tCLCL +2 ns minimum 2/3 tCLCL -15 ns minimum 10 ns maximum tCLCL -20 ns minimum tCLCL -20 ns minimum 2/3 tCLCL -15 ns minimum
As shown above, the MSM82C84A-2 satisfies the characteristics (except for Input Rise/Fall Time) of the MSM82C84A. 1) MSM82C84A-5 and MSM82C84A-2
Parameter EFI High Time EFI Low Time EFI Period Crystal Frequency CLK Period Symbol tEHEL tELEH tELEL -- tCHCL MSM82C84A-5 20 ns minimum 20 ns minimum 66 ns minimum 15 MHz maximum 200 ns minimum MSM82C84A-2 13 ns minimum 17 ns minimum 36 ns minimum 24 MHz maximum 125 ns minimum
As shown above, the MSM82C84A-2 satisfies the characteristics of the MSM82C84A-5.
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4) Notices on use
MSM82C84A-2RS/GS/JS
Note the following when replacing devices as the ASYNC pin is differently treated between the MSM82C84A and the MSM82C84A-5/MSM82C84A-2: Case 1: When only a pullup resistor is externally connected to. The MSM82C84A can be replaced by the MSM82C84A-2. Case 2: When only pulldown resistor is externally connected to. When the pulldown resistor is 8 kiloohms or less, the MSM82C84A can be replaced by the MSM82C84A-2. When the pulldown resistor is greater than 8 kiloohms, use a pulldown resistor of 8 kiloohms or less. Case 3: When an output of the other IC device is connected to the device. The MSM82C84A can be replaced by the MSM82C84A-2 when the IOL pin of the device to drive the ASYNC pin of the MSM82C84A-2 has an allowance of 100 mA or more.
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PACKAGE DIMENSIONS
(Unit : mm)
DIP18-P-300-2.54
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 1.30 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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MSM82C84A-2RS/GS/JS
(Unit : mm)
QFJ20-P-S350-1.27
Spherical surface
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin Cu alloy Solder plating 5 mm or more 0.59 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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MSM82C84A-2RS/GS/JS
(Unit : mm)
SOP24-P-430-1.27-K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.58 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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